1. Field of the Invention
The present invention relates generally to the deposition of structures and more specifically to the deposition of three-dimensional solid structures of controlled geometry at a specified point or points on a substrate surface.
2. Description of the Background Art
The controlled deposition of three-dimensional structures, with high spatial resolution, is desirable for various applications. These applications include the microfabrication of field emitter arrays, quantum dots, electrical contacts and microcircuits and other devices and components.
For example, the Field Emitter Array (FEA) is a microfabricated array of very small field emission sources and integrated extraction apertures. FEAs are significant for technology because they allow for the production of free electrons in a compact and manufacturable form, because the emission may be voltage modulated at high frequency and low voltage, and because they can have higher brightness, current density and total current than other types of electron sources. A number of device applications of great significance to the Navy and industry have been suggested, including flat panel displays and high frequency amplifiers. Current FEA fabrication technologies appear to be good enough to allow commercial production of flat panel cathodoluminescent displays, and an RF device demonstration effort is underway. However, improvements in a number of FEA properties would allow improved device characteristics.
An FEA may have either a vertical or a horizontal geometry. In both cases, the emitter structures may be either points (tips), edges, wedges, or other sharp structures. Edge structures are often much easier to fabricate than are points. All FEA designs must incorporate a non-intercepting electrode, called the gate, which is used to produce and modulate a high electric field at the emitter surface. A sharp emitter structure is located inside the aperture or slot, such that the field is concentrated at the sharp emitter tip or edge. Most applications benefit when the ratio of the field at the apex of the emitter to the voltage applied to the gate (.beta.=F/V) is maximized. .beta. can be increased by reducing the size of the aperture and reducing the radius of curvature of the emitter. Point shaped emitters concentrate the field in almost three dimensions, whereas edges concentrate the field in only two dimensions. Thus point geometries will typically produce the highest .beta.'s. Large values of .beta. reduce the power and voltage needed to operate FEA devices, and reduce the risk of failures due to dielectric breakdown or arcing. Present FEA fabrication techniques are producing emitter tips with radii near or below 100 .ANG.. Applications which require high modulation frequency require low capacitance as well as high .beta.. In particular, high frequency applications require a maximum ratio of transconductance to capacitance, achieved through a combination of high .beta., low emitter work function, high current density, high aspect ratio, large number of emitters, and geometry of field emitter and gate electrode. Many situations would also benefit from one or more additional apertures to accelerate, focus, or deflect the emitted beam. Most proposed FEA applications require a large number of emitters to produce sufficient current. If the current density must be high, or the capacitance must be low, it is important that a large fraction of the emitters in an array produce high current levels.
To achieve technologically significant levels of performance, new and innovative FEA fabrication methods and materials are required. The very sharp tip radii must be achieved through mechanisms such as etching, deposition, or growth, rather than direct lithography. Applications requiring the best possible emission transconductance demand that the emitting material have a low work function, reasonably inert surface, high electrical and thermal conductivity, as well as a very small radius of curvature. The maximum current density tolerated at the emitter tip should also be exceptionally high, up to 10.sup.8 A/cm.sup.2, hence the bond strength, molecular weight, thermal conductivity, and fracture strength are important properties of the emitter material. In some applications the dielectric supporting the aperture must have high thermal conductivity, an ability to shed intercepted electrons, and good high temperature properties as well as high breakdown strength. Thus fabrication methods which allow the use of high quality materials are important for demanding applications.
Also, integrated circuits, such as a microprocessor, require connections to both power supplies and logic circuits. As the number of connections increases, so does the need for small, inexpensive contacts. The method of the present invention can provide contact structures, with high spatial resolution, at specific locations along the surface of an integrated circuit. When a contact structure of high aspect ratio and controlled angle of sharpness contacts the circuit, the insertion pressure causes the tip of the contact structure to scratch away or pierce any oxide coating that has built up at the contact point of the board, as well as pierce the underlying metal to be contacted. This scratching and piercing causes the formation of an electrical and physical contact. The sharpness and the high aspect ratio allow multiple, in plane contacts to made simultaneously, without non-contacting gaps due to local non-flatness.
Additionally, even where a sharp structure is not needed, the deposition of a material in a highly controllable manner is useful in the manufacture of quantum dot structures, and other devices and components that require the microfabrication of patterns with high spatial resolution.